rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 8-bit dac with output amplifiers ad7224 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram features 8-bit cmos dac with output amplifiers operates with single or dual supplies low total unadjusted error: less than 1 lsb over temperature extended temperature range operation m p-compatible with double buffered inputs standard 18-pin dips, and 20-terminal surface mount package and soic package product highlights 1. dac and amplifier on cmos chip the single-chip design of the 8-bit dac and output amplifier is inherently more reliable than multi-chip designs. cmos fabrication means low power consumption (35 mw typical with single supply). 2. low total unadjusted error the fabrication of the ad7224 on analog devices linear compatible cmos (lc 2 mos) process coupled with a novel dac switch-pair arrangement, enables an excellent total un- adjusted error of less than 1 lsb over the full operating tem- perature range. 3. single or dual supply operation the voltage-mode configuration of the ad7224 allows opera- tion from a single power supply rail. the part can also be op- erated with dual supplies giving enhanced performance for some parameters. 4. versatile interface logic the high speed logic allows direct interfacing to most micro- processors. additionally, the double buffered interface en- ables simultaneous update of the ad7224 in multiple dac systems. the part also features a zero override function. general description the ad7224 is a precision 8-bit voltage-output, digital-to- analog converter, with output amplifier and double buffered interface logic on a monolithic cmos chip. no external trims are required to achieve full specified performance for the part. the double buffered interface logic consists of two 8-bit regis- tersCan input register and a dac register. only the data held in the dac registers determines the analog output of the con- verter. the double buffering allows simultaneous update in a system containing multiple ad7224s. both registers may be made transparent under control of three external lines, cs , wr and ldac . with both registers transparent, the reset line functions like a zero override; a useful function for system cali- bration cycles. all logic inputs are ttl and cmos (5 v) level compatible and the control logic is speed compatible with most 8-bit microprocessors. specified performance is guaranteed for input reference voltages from +2 v to +12.5 v when using dual supplies. the part is also specified for single supply operation using a reference of +10 v. the output amplifier is capable of developing +10 v across a 2 k w load. the ad7224 is fabricated in an all ion-implanted high speed linear compatible cmos (lc 2 mos) process which has been specifically developed to allow high speed digital logic circuits and precision analog circuits to be integrated on the same chip.
rev. b C2C ad7224Cspecifications (v dd = 11.4 v to 16.5 v, v ss = C5 v 6 10%; agnd = dgnd = o v; v ref = +2 v to (v dd C 4 v) 1 unless otherwise noted. all specifications t min to t max unless otherwise noted.) dual supply k, b, t l, c, u parameter versions 2 versions 2 units conditions/comments static performance resolution 8 8 bits total unadjusted error 2 1 lsb max v dd = +15 v 5%, v ref = +10 v relative accuracy 1 1/2 lsb max differential nonlinearity 1 1 lsb max guaranteed monotonic full-scale error 3/2 1 lsb max full-scale temperature coefficient 20 20 ppm/ c max v dd = 14 v to 16.5 v, v ref = +10 v zero code error 30 20 mv max zero code error temperature coefficient 50 30 m v/ c typ reference input voltage range 2 to (v dd C 4) 2 to (v dd C 4) v min to v max input resistance 8 8 k w min input capacitance 3 100 100 pf max occurs when dac is loaded with all 1s. digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input leakage current 1 1 m a max v in = 0 v or v dd input capacitance 3 8 8 pf max input coding binary binary dynamic performance voltage output slew rate 3 2.5 2.5 v/ m s min voltage output settling time 3 positive full-scale change 5 5 m s max v ref = +10 v; settling time to 1/2 lsb negative full-scale change 7 7 m s max v ref = +10 v; settling time to 1/2 lsb digital feedthrough 50 50 nv secs typ v ref = 0 v minimum load resistance 2 2 k w min v out = +10 v power supplies v dd range 11.4/16.5 11.4/16.5 v min/v max for specified performance v ss range 4.5/5.5 4.5/5.5 v min/v max for specified performance i dd @ 25 c 4 4 ma max outputs unloaded; v in = v inl or v inh t min to t max 6 6 ma max outputs unloaded; v in = v inl or v inh i ss @ 25 c 3 3 ma max outputs unloaded; v in = v inl or v inh t min to t max 5 5 ma max outputs unloaded; v in = v inl or v inh switching characteristics 3, 4 t 1 @ 25 c 90 90 ns min chip select/load dac pulse width t min to t max 90 90 ns min t 2 @ 25 c 90 90 ns min write/reset pulse width t min to t max 90 90 ns min t 3 @ 25 c 0 0 ns min chip select/load dac to write setup time t min to t max 0 0 ns min t 4 @ 25 c 0 0 ns min chip select/load dac to write hold time t min to t max 0 0 ns min t 5 @ 25 c 90 90 ns min data valid to write setup time t min to t max 90 90 ns min t 6 @ 25 c 10 10 ns min data valid to write hold time t min to t max 10 10 ns min notes 1 maximum possible reference voltage. 2 temperature ranges are as follows: k, l versions: C40 c to +85 c b, c versions: C40 c to +85 c t, u versions: C55 c to +125 c 3 sample tested at 25 c by product assurance to ensure compliance. 4 switching characteristics apply for single and dual supply operation. specifications subject to change without notice.
ad7224 rev. b C3C single supply k, b, t l, c, u parameter versions 2 versions 2 units conditions/comments static performance resolution 8 8 bits total unadjusted error 2 2 lsb max differential nonlinearity 1 1 lsb max guaranteed monotonic reference input input resistance 8 8 k w min input capacitance 3 100 100 pf max occurs when dac is loaded with all 1s. digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input leakage current 1 1 m a max v in = 0 v or v dd input capacitance 3 8 8 pf max input coding binary binary dynamic performance voltage output slew rate 4 22v/ m s min voltage output settling time 4 positive full-scale change 5 5 m s max settling time to 1/2 lsb negative full-scale change 20 20 m s max settling time to 1/2 lsb digital feedthrough 3 50 50 nv secs typ v ref = 0 v minimum load resistance 2 2 k w min v out = +10 v power supplies v dd range 14.25/15.75 14.25/15.75 v min/v max for specified performance i dd @ 25 c 4 4 ma max outputs unloaded; v in = v inl or v inh t min to t max 6 6 ma max outputs unloaded; v in = v inl or v inh switching characteristics 3, 4 t 1 @ 25 c 90 90 ns min chip select/load dac pulse width t min to t max 90 90 ns min t 2 @ 25 c 90 90 ns min write/reset pulse width t min to t max 90 90 ns min t 3 @ 25 c 0 0 ns min chip select/load dac to write setup time t min to t max 0 0 ns min t 4 @ 25 c 0 0 ns min chip select/load dac to write hold time t min to t max 0 0 ns min t 5 @ 25 c 90 90 ns min data valid to write setup time t min to t max 90 90 ns min t 6 @ 25 c 10 10 ns min data valid to write hold time t min to t max 10 10 ns min notes 1 maximum possible reference voltage. 2 temperature ranges are as follows: ad7224kn, ln: 0 c to +70 c ad7224bq, cq: C25 c to +85 c ad7224td, ud: C55 c to +125 c 3 see terminology. 4 sample tested at 25 c by product assurance to ensure compliance. specifications subject to change without notice. (v dd = +15 v 6 5%; v ss = agnd = dgnd = o v; v ref = +10 v 1 unless otherwise noted. all specifications t min to t max unless otherwise noted.)
ad7224 rev. b C4C absolute maximum ratings 1 v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +17 v v dd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +17 v v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, +24 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd digital input voltage to dgnd . . . . . . . C0.3 v, v dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . . . . . . C0.3 v, v dd + 0.3 v v out to agnd 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss , v dd power dissipation (any package) to +75 c . . . . . . . . 450 mw derates above 75 c by . . . . . . . . . . . . . . . . . . . . . 6 mw/ c operating temperature commercial (k, l versions) . . . . . . . . . . . C40 c to +85 c industrial (b, c versions) . . . . . . . . . . . . . C40 c to +85 c extended (t, u versions) . . . . . . . . . . . . C55 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 secs) . . . . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 the outputs may be shorted to agnd provided that the power dissipation of the package is not exceeded. typically short circuit current to agnd is 60 ma. ordering guide total temperature unadjusted package model 1 range error (lsb) option 2 ad7224kn C40 c to +85 c 2 max n-18 ad7224ln C40 c to +85 c 1 max n-18 ad7224kp C40 c to +85 c 2 max p-20a ad7224lp C40 c to +85 c 1 max p-20a ad7224kr-1 C40 c to +85 c 2 max r-20 ad7224lr-1 C40 c to +85 c 1 max r-20 ad7224kr-18 C40 c to +85 c 2 max r-18 AD7224LR-18 C40 c to +85 c 1 max r-18 ad7224bq C40 c to +85 c 2 max q-18 ad7224cq C40 c to +85 c 1 max q-18 ad7224tq C55 c to +125 c 2 max q-18 ad7224uq C55 c to +125 c 1 max q-18 ad7224te C55 c to +125 c 2 max e-20a ad7224ue C55 c to +125 c 1 max e-20a notes 1 to order mil-std-883 processed parts, add /883b to part number. contact your local sales office for military data sheet. 2 e = leadless ceramic chip carrier; n = plastic dip; p = plastic leaded chip carrier; q = cerdip; r = soic. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7224 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin configurations dip and soic (soic) (soic) v ss v out v dd reset dgnd (msb) db7 db6 db0 (lsb) db1 v ref agnd ldac db5 db2 db4 db3 cs wr 1 2 18 17 5 6 7 14 13 12 3 4 16 15 811 910 top view (not to scale) ad7224 v ss v out v dd reset dgnd (msb) db7 db6 db0 (lsb) db1 v ref agnd ldac db5 db2 db4 db3 cs wr 1 2 18 17 5 6 7 14 13 12 3 4 16 15 811 9 10 top view (not to scale) ad7224 r-18 nc = no connect v ss v out v dd reset dgnd (msb) db7 db6 cs db0 (lsb) db1 v ref agnd ldac wr db5 db2 db4 db3 nc nc 1 2 20 19 5 6 7 16 15 14 3 4 18 17 8 13 9 12 10 11 top view (not to scale) ad7224 r-20 lccc plcc nc = no connect v ref agnd db6 dgnd (msb) db7 v out v ss reset nc v dd db5 db4 db2 nc db3 ldac wr db1 cs db0 (lsb) 19 3 1 220 4 5 8 6 7 12 13 911 10 18 17 14 16 15 top view (not to scale) ad7224 nc = no connect v ref agnd db6 dgnd (msb) db7 v out v ss reset nc v dd db5 db4 db2 nc db3 ldac wr db1 cs db0 (lsb) 19 31 2 20 4 5 8 6 7 12 13 9 11 10 18 17 14 16 15 top view (not to scale) ad7224
ad7224 rev. b C5C v out = d ? v ref where d is a fractional representation of the digital input code and can vary from 0 to 255/256. op-amp section the voltage-mode d/a converter output is buffered by a unity gain noninverting cmos amplifier. this buffer amplifier is capable of developing +10 v across a 2 k w load and can drive capacitive loads of 3300 pf. the ad7224 can be operated single or dual supply resulting in different performance in some parameters from the output am- plifier. in single supply operation (v ss = 0 v = agnd) the sink capability of the amplifier, which is normally 400 m a, is reduced as the output voltage nears agnd. the full sink capability of 400 m a is maintained over the full output voltage range by tying v ss to C5 v. this is indicated in figure 2. 500 0 10 300 100 2 200 0 400 8 6 4 v out ?volts i sink ? m a v ss = ?v v ss = 0v v dd = +15v t a = 25 c figure 2. variation of i sink with v out settling-time for negative-going output signals approaching agnd is similarly affected by v ss . negative-going settling-time for single supply operation is longer than for dual supply opera- tion. positive-going settling-time is not affected by v ss . additionally, the negative v ss gives more headroom to the out- put amplifier which results in better zero code performance and improved slew-rate at the output, than can be obtained in the single supply mode. digital section the ad7224 digital inputs are compatible with either ttl or 5 v cmos levels. all logic inputs are static-protected mos gates with typical input currents of less than 1 na. internal in- put protection is achieved by an on-chip distributed diode be- tween dgnd and each mos gate. to minimize power supply currents, it is recommended that the digital input voltages be driven as close to the supply rails (v dd and dgnd) as practi- cally possible. interface logic information table i shows the truth table for ad7224 operation. the part contains two registers, an input register and a dac register. cs and wr control the loading of the input register while ldac and wr control the transfer of information from the input regis- ter to the dac register. only the data held in the dac register will determine the analog output of the converter. all control signals are level-triggered and therefore either or both registers may be made transparent; the input register by keeping cs and wr low, the dac register by keeping ldac and wr low. input data is latched on the rising edge of wr . terminology total unadjusted error total unadjusted error is a comprehensive specification which includes full-scale error, relative accuracy and zero code error. maximum output voltage is v ref C 1 lsb (ideal), where 1 lsb (ideal) is v ref /256. the lsb size will vary over the v ref range. hence the zero code error, relative to the lsb size, will increase as v ref decreases. accordingly, the total unadjusted error, which includes the zero code error, will also vary in terms of lsbs over the v ref range. as a result, total unadjusted error is specified for a fixed reference voltage of +10 v. relative accuracy relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after al- lowing for zero code error and full-scale error and is normally expressed in lsbs or as a percentage of full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb max over the operating temperature range ensures monotonicity. digital feedthrough digital feedthrough is the glitch impulse transferred to the out- put due to a change in the digital input code. it is specified in nv secs and is measured at v ref = 0 v. full-scale error full-scale error is defined as: measured value C zero code error C ideal value circuit information d/a section the ad7224 contains an 8-bit voltage-mode digital-to-analog converter. the output voltage from the converter has the same polarity as the reference voltage, allowing single supply opera- tion. a novel dac switch pair arrangement on the ad7224 al- lows a reference voltage range from +2 v to +12.5 v. the dac consists of a highly stable, thin-film, r-2r ladder and eight high speed nmos single pole, double-throw switches. the simplified circuit diagram for this dac is shown in figure 1. v out rrr 2r 2r 2r 2r 2r db0 db0 db0 db0 v ref agnd shown for all 1's on dac figure 1. d/a simplified circuit diagram the input impedance at the v ref pin is code dependent and can vary from 8 k w minimum to infinity. the lowest input imped- ance occurs when the dac is loaded with the digital code 01010101. therefore, it is important that the reference presents a low output impedance under changing load conditions. the nodal capacitance at the reference terminals is also code depen- dent and typically varies from 25 pf to 50 pf. the v out pin can be considered as a digitally programmable voltage source with an output voltage of:
ad7224 rev. b C6C table i. ad7224 truth table reset ldac wr cs function h l l l both registers are transparent h x h x both registers are latched h h x h both registers are latched h h l l input register transparent hh g l input register latched h l l h dac register transparent hl g h dac register latched l x x x both registers loaded with all zeros g h h h both register latched with all zeros and output remains at zero g l l l both registers are transparent and output follows input data h = high state, l = low state, x = dont care. all control inputs are level triggered. the contents of both registers are reset by a low level on the reset line. with both registers transparent, the reset line functions like a zero override with the output brought to 0 v for the duration of the reset pulse. if both registers are latched, a low pulse on reset will latch all 0s into the registers and the output remains at 0 v after the reset line has returned high. the reset line can be used to ensure power-up to 0 v on the ad7224 output and is also useful, when used as a zero override, in system calibration cycles. figure 3 shows the input control logic for the ad7224. input data ldac wr cs reset dac register input register figure 3. input control logic t 2 t 1 t 2 t 1 t 4 t 3 t 3 t 4 data valid t 5 t 6 data in cs wr ldac notes: 1. all input signal rise and fall times measured from 10% to 90% of v dd . t r = t f = 20ns over v dd range 2. timing measurement reference level is v inh + v inl 2 figure 4. write cycle timing diagram specification ranges for the dac to maintain specified accuracy, the reference volt- age must be at least 4 v below the v dd power supply voltage. this voltage differential is required for correct generation of bias voltages for the dac switches. with dual supply operation, the ad7224 has an extended v dd range from +12 v 5% to +15 v 10% (i.e., from +11.4 v to +16.5 v). operation is also specified for a single v dd power supply of +15 v 5%. performance is specified over a wide range of reference voltages from 2 v to (v dd C 4 v) with dual supplies. this allows a range of standard reference generators to be used such as the ad580, a +2.5 v bandgap reference and the ad584, a precision +10 v reference. note that in order to achieve an output voltage range of 0 v to +10 v, a nominal +15 v 5% power supply voltage is required by the ad7224. ground management ac or transient voltages between agnd and dgnd can cause noise at the analog output. this is especially true in micropro- cessor systems where digital noise is prevalent. the simplest method of ensuring that voltages at agnd and dgnd are equal is to tie agnd and dgnd together at the ad7224. in more complex systems where the agnd and dgnd intertie is on the backplane, it is recommended that two diodes be con- nected in inverse parallel between the ad7224 agnd and dgnd pins (in914 or equivalent). applying the ad7224 unipolar output operation this is the basic mode of operation for the ad7224, with the output voltage having the same positive polarity as v ref . the ad7224 can be operated single supply (v ss = agnd) or with positive/negative supplies (see op-amp section which outlines the advantages of having negative v ss ). connections for the uni- polar output operation are shown in figure 5. the voltage at v ref must never be negative with respect to dgnd. failure to observe this precaution may cause parasitic transistor action and possible device destruction. the code table for unipolar output operation is shown in table ii. dac db7 db0 3 v dd v ref cs wr ldac reset v ss agnd dgnd ad7224 v out data (8-bit) figure 5. unipolar output circuit table iii. unipolar code table dac register contents msb lsb analog output 1 1 1 1 1 1 1 1 + v ref 255 256 ? ? ? ? 1 0 0 0 0 0 0 1 + v ref 129 256 ? ? ? ? 1 0 0 0 0 0 0 0 + v ref 128 256 ? ? ? ? =+ v ref 2 0 1 1 1 1 1 1 1 + v ref 127 256 ? ? ? ? 0 0 0 0 0 0 0 1 + v ref 1 256 ? ? ? ? 0 0 0 0 0 0 0 0 0 v note : 1 lsb = v ref () 2 - 8 () = v ref 1 256 ? ? ? ?
ad7224 rev. b C7C bipolar output operation the ad7224 can be configured to provide bipolar output op- eration using one external amplifier and two resistors. figure 6 shows a circuit used to implement offset binary coding. in this case v o = 1 + r 2 r 1 ? ? ? ? d v ref () r 2 r 1 ? ? ? ? v ref () with r 1 = r 2 v o = (2 d C 1) ? v ref where d is a fractional representation of the digital word in the dac register. mismatch between r1 and r2 causes gain and offset errors; therefore, these resistors must match and track over tempera- ture. once again, the ad7224 can be operated in single supply or from positive/negative supplies. table iii shows the digital code versus output voltage relationship for the circuit of figure 6 with r1 = r2. +15v +15v v ref r1 r2 v out r1, r2 = 10k w 0.1% dac db7 db0 3 v dd v ref cs wr ldac reset v ss agnd dgnd ad7224 v out data (8-bit) figure 6. bipolar output circuit table iii. bipolar (offset binary) code table dac register contents msb lsb analog output 1 1 1 1 1 1 1 1 + v ref 127 128 ? ? ? ? 1 0 0 0 0 0 0 1 + v ref 1 128 ? ? ? ? 1 0 0 0 0 0 0 0 0 v 0 1 1 1 1 1 1 1 v ref 1 128 ? ? ? ? 0 0 0 0 0 0 0 1 v ref 127 128 ? ? ? ? 0 0 0 0 0 0 0 0 v ref 128 128 ? ? ? ? = v ref agnd bias the ad7224 agnd pin can be biased above system gnd (ad7224 dgnd) to provide an offset zero analog output voltage level. figure 7 shows a circuit configuration to achieve this. the output voltage, v out , is expressed as: v out = v bias + d ? ( v in ) where d is a fractional representation of the digital word in dac register and can vary from 0 to 255/256. for a given v in , increasing agnd above system gnd will re- duce the effective v dd Cv ref which must be at least 4 v to en- sure specified operation. note that v dd and v ss for the ad7224 must be referenced to dgnd. dac v dd v ref v ss agnd dgnd ad7224 v out v in v in v bias figure 7. agnd bias circuit microprocessor interface 8085a 8088 a15 a8 ale ad0 ad7 address decode latch en ad7224* wr db7 db0 ldac wr address bus address data bus *linear circuitry omitted for clarity cs figure 8. ad7224 to 8085a/8088 interface d0 d7 data bus *linear circuitry omitted for clarity e or f 2 d0 d7 e or f 2 r/w a15 a0 6809 6502 address decode en address bus ldac wr cs db7 db0 ad7224* figure 9. ad7224 to 6809/6502 interface z-80 a15 a0 d0 d7 ad7224* db7 db0 ldac wr address bus data bus *linear circuitry omitted for clarity address decode cs wr figure 10. ad7224 to z-80 interface 68008 a23 a1 d0 d7 ad7224* db7 db0 ldac wr address bus data bus *linear circuitry omitted for clarity address decode cs r/w dtack figure 11. ad7224 to 68008 interface
ad7224 rev. b C8C outline dimensions dimensions shown in inches and (mm). c836aC10C10/84 printed in u.s.a. 18-pin plastic (suffix n) 18-pin ceramic (suffix d) plcc package p-20a 0.048 (1.21) 0.042 (1.07) 0.356 (9.04) 0.350 (8.89) sq 0.395 (10.02) 0.385 (9.78) sq 0.048 (1.21) 0.042 (1.07) 0.050 (1.27) bsc 0.020 (0.50) r 19 3 top view 18 14 9 8 pin 1 identifier 4 13 0.110 (2.79) 0.085 (2.16) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.040 (1.01) 0.025 (0.64) 0.180 (4.57) 0.165 (4.19) 0.330 (8.38) 0.290 (7.37) lccc package e-20a 0.358 (9.09) max sq 0.088 (2.24) 0.054 (1.37) 0.100 (2.54) 0.064 (1.63) 0.358 (9.09) 0.342 (8.69) sq 0.075 (1.91) ref 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ bottom view 0.015 (0.38) min 1 20 13 9 0.028 (0.71) 0.022 (0.56) 0.095 (2.41) 0.075 (1.90) 0.200 (5.08) bsc 0.100 (2.54) bsc 0.055 (1.40) 0.045 (1.14) 45 typ 0.150 (3.81) bsc 0.050 (1.27) bsc 18-pin cerdip (suffix q) 18-lead soic (r-18) pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 18 10 9 0.4625 (11.75) 0.4469 (11.35) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.1043 (2.65) 0.0926 (2.35) 0.0118 (0.30) 0.0040 (0.10) 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 20-lead soic (r-20) pin 1 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 1 20 11 10 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 0 0.0291 (0.74) 0.0098 (0.25) x 45 0.5118 (13.00) 0.4961 (12.60) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35)
|
